1. Field of the Invention
The present invention relates to a method of and an apparatus for processing information, and a providing medium, and more particularly to a method of and an apparatus for processing information to be able to associate one logical address with numbers of bits making up one word on a physical address for reading and writing words made up of different numbers of bits according to common address management, and a providing medium for providing a program and/or data to carry out such a method.
2. Description of the Related Art
Information processing apparatus, e.g., personal computers, require a large-scale main memory for storing a program if the program is large in size. However, there is a limitation on the storage capacity of such a main memory, and a main memory having a storage capacity large enough to store a large program may not necessarily be available.
One solution to the above problems is to use a virtual memory that produces an apparent storage space larger than the storage space of a main memory. The user can use the virtual memory as if the apparent storage space were actually present for data storage.
Addresses used by the virtual memory are referred to as virtual addresses or logical addresses. Addresses used by the main memory are referred to as real addresses or physical addresses.
FIG. 6 of the accompanying drawings shows a conventional information processing apparatus. A process of converting a logical address into a physical address when a controller 70 reads data stored in a main memory 74 will be described below with reference to FIG. 6. The number of bits of each word of data handled by the controller 70 is fixed to xe2x80x9c16xe2x80x9d, for example. Even with the fixed number of bits assigned to each word, it is possible that 16 bits are treated as one word, 8 bits as half word, and 32 bits as double word. Each word of data handled by the main memory 74 is also fixed to a certain number of bits, though the main memory 74 is also capable of treating different numbers of bits.
When the controller 70 reads data stored in the main memory 74, the controller 70 outputs a logical address to a bit decision unit 71, which determines the type of data that the entered logical address belongs to, i.e., how many bits make up one word of data that the entered logical address belongs to. The bit decision unit 71 then outputs the result of the decision and the logical address to a mode converter 72. Depending on the result of the decision, the mode converter 72 selects a mode (program) for converting a logical address into a physical address. If the bit decision unit 71 determines that one word is made up of 32 bits, then the mode converter 72 selects a 32-bit mode. If the bit decision unit 71 determines that one word is made up of 16 bits, then the mode converter 72 selects a 16-bit mode.
After the mode converter 72 has selected a mode for converting a logical address into a physical address, an address indicator 73 calculates a physical address using the selected mode and the logical address, and supplies the calculated physical address to the main memory 74. The main memory 74 reads data at the supplied physical address and supplies the data to the controller 70.
In this manner, the logical address is converted into the physical address after the mode corresponding to the number of bits of one word of data that the logical address belongs to has been selected.
If words made up of different numbers of bits are used, then the conventional information processing apparatus needs to change modes for reading data from physical addresses based on logical addresses, and cannot quickly generate physical addresses from logical addresses.
It is therefore an object of the present invention to determine physical addresses based on base addresses of logical addresses for quickly generating physical addresses for words of different sizes.
The above and other objects, features, and advantages of the present invention will become more apparent from the following description when taken in conjunction with the accompanying drawings in which a preferred embodiment of the present invention is shown by way of example.